1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming the self-aligned channel profile for a CMOS device using a gate poly reverse mask.
2) Description of the Prior Art
The continued scaling of MOSFET gate lengths to submicron dimensions aggravates the problems of high gate resistance, polysilicon gate depletion and increased gate tunnel leakage. One method to overcome the problems of short channel effects is to use through-the-gate implantation. Channel implants are formed by implanting ions through the gate structure to form a doped region below the substrate surface in the gate area. Through-the-gate implantation can achieve the steep retrograde doping profiles, which can improve the short channel effects and increase current drivability. However, the implantation is difficult to control.
Another method used is the pocket implant. A localized ion implant is performed beneth the substrate surface in the gate area. This can be done using a photoresist mask. The pocket implant technology has greater reverse short channel effect because the LDD implant dose is increased to compensate for the channel dopant.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents and articles.
U.S. Pat. No. 5,444,008 (Han et al.) shows a high-performance punchthrough implant method for MOS/VLSI using an image reversal photo lithography method. In this invention the positive photoresist layer is formed on the substrate and patterend by means of image reversal photo lithography to form an appature. P-type ions are implanted through the appature to form an anti-punchthrough implant below the subsequently formed gate.
U.S. Pat. No. 5,686,321 (Ko et al.) shows a method for forming a self-aligned punchthrough stop region using a blanket implant, forming an implant mask with a gate opening, forming spacers at the edge of the opening, performing a punchthrough implant, removing the implant mask, and forming source and drain regions.
U.S. Pat. No. 5,915,181 (Tseng) show a process for fabricating a deep submicron MOSFET device using a self-aligned threshold voltage adjust region.
U.S. Pat. No. 5,918,130 (Hause et al.) shows a method for preforming source and drain implants and forming silicide contacts prior to anti-punchtrough implant and gate formation.
U.S. Pat. No. 5,688,700 (Kao et al.) and U.S. Pat. No. 5,447,874 (Grivna et al.) show methods for forming a field effect transistor using a self aligned doped implant region under the channel.
U.S. Pat. No. 5,792,699 (Tsui) shows a method for reduction of reverse short channel effect in MOSFET using a channel ion implant through the gate after the source and drain are formed and its damage annealed out.
Channel Profile Engineering of 0.1 Micron Silicon MOSFET by Through-the-Gate Implantation by Y. V. Ponomarev et al. teaches that the short channel effects can be improved by the use of super-steep retrograde (SSR) doping profiles. This SSR channel profile is preferably achieved for NMOST""s by through-the-gate implantation.
Sub-100 nm Gate Lenth Metal Gate NMOS Transistors Fabricated by Replacement Gate Process by A. Chatterjee et al. teaches a process of fabricating a NMOS transistor using self-aligned source and drain using a replacement gate process to prevent high tempature processing of gate materials during source and drain anneal.
It is an object of the present invention to provide a method for forming a channel implant using a gate poly reverse mask.
It is another object of the present invention to provide a method for forming a channel implant with a lower threshhold voltage roll-off than a through the gate implant and without reverse short channel effects like a pocket implant.
To accomplish the above objectives, the present invention provides a method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a threshhold voltage adjust region and an anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the gate layer is planarized to form a first gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
The present invention provides considerable improvement over the prior art. Most importantly, the present invention provides a channel implant which can provide a lower threshhold voltage roll-off than a through the gate implant, without a reverse short channel effect as in a pocket implant. Also, the present invention can use existing photolithography reticles to form reverse gate poly masks.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.